This invention relates to power MOSFET devices and their methods of manufacture, and more specifically relates to such devices with reduced RDSON, reduced gate capacitance and increased gate breakdown voltage.
In present trench type power MOSFET devices, a vertical gate oxide is formed simultaneously within the vertical walls of the trench and at the trench bottom. In order to provide a low RDSON, the vertical oxide should be relatively thin. However, the gate to drain capacitance is determined by the thickness of the gate oxide at the trench bottom, and the gate breakdown voltage VGSMAX is limited by the curvatures of the oxide at the trench bottom corner. Thus, the desire for a thin vertical gate oxide for low RDSON is contradictory to the need of a thick oxide at the bottom of the trench for improved VGSMAX and a low gate to drain capacitance. It would be desirable to harmonize these trade-offs.
A further problem exists in present trench type power MOSFETS due to the conventional formation of the channel and source diffusions. Thus, these regions are usually formed by an implant followed by the diffusion. The implants are known to cause surface damage which extends to a particular depth, depending on the process variables. Therefore, the vertical channel, which extends from the point at which the source intersects the trench wall to the bottom of the channel diffusion, will include damaged silicon caused by the earlier implants. This then increases threshold voltage and increases the channel resistance. It would be desirable to avoid the influence of implant damage on the conduction channel of the device.
A still further problem exists in current power MOSFETs in that the inherent Miller capacitance of the structure increases the gate charge QG of the device and thus increases switching loss. It would be desirable to reduce Miller capacitance to reduce switching loss.
In accordance with a first aspect of this invention, a novel structure and process are provided which result in the production of a thick gate oxide at the bottom of the trench and a significantly thinner gate oxide along its vertical wall. Thus, a trench is first etched in conventional fashion, through a source diffusion layer and channel diffusion layer and the trench walls and bottom have a silicon nitride coating deposited thereon. A thermally grown pad oxide may be formed before depositing the silicon nitride. The silicon nitride at the bottom surface of the trench is then reactively etched away, and a silicon dioxide layer is then grown on the exposed silicon at the bottom of the trench. The bottom oxide layer is grown to any desired thickness, for example, 1000 xc3x85 to 1400 xc3x85 in comparison to the conventional oxide thickness of about 320 xc3x85 used for the side wall gate oxide in the conventional device. During its growth, the oxide and the silicon at the corners of the trench round out to smooth or round the otherwise sharp bottom corners of the trench.
In another embodiment of the invention, the thicker bottom oxide is formed by amorphizing the trench bottom by using a heavy dose ion implantation (for example 1E16 atoms/cm2) of a neutral species ion, for example, Argon, after the trench etch. This process makes use of the fact that amorphized silicon oxidizes 3 or 4 times faster than the single crystal silicon surface along the vertical trench walls.
Thereafter, the silicon nitride layer remaining on the trench walls is removed by a wet etch which leaves the thick bottom oxide layer intact. A thin gate oxide (320 xc3x85 for example) is then grown on the exposed side walls.
The resulting structure has the desired thick bottom oxide and rounded silicon bottom for increased VDSMAX and VGSMAX and reduced Miller capacitance; and a thin gate oxide on the trench walls for reduced RDSON.
The channel length of the new device is also reduced to about 0.7 microns (from 1.2 microns for the same voltage in the prior art).
In forming the source and channel diffusions, the impurity atoms are implanted into the silicon and diffused before forming the trench. When the diffusions are shallow, as for a low voltage device with a reduced channel length (for example, 0.5 microns) part of the blocking voltage is held off only by the channel. However, the channel may include silicon along the trench wall which was damaged during the implant process. In accordance with a further feature of the invention, the source diffusion in a short channel low voltage MOSFET is made intentionally deeper than the implant damage depth. In this way, the full channel length will be along undamaged silicon so that threshold voltage and RDSON characteristics are unaffected by silicon crystal implant damage.
As a still further feature of the invention, and to further reduce Miller capacitance, a very lightly doped Pxe2x88x92xe2x88x92 or Nxe2x88x92xe2x88x92 diffusion of about 1000 xc3x85 to about 2000 xc3x85 in depth is formed around the bottom of the trench. The Pxe2x88x92xe2x88x92 diffusion will be depleted at all times by the inherent junction voltage, thus reducing Miller capacitance and switching loss. This concept is applicable to planer devices as well as trench devices.